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Mar 19

Some myths around UVM & SVA

We at CVC deal with all sorts of verification technologies, languages, standards and tools. It is interesting to see time and again how easy it is (especially for junior engineers) to get bogged down with the complexity of language/methodology and loose the big picture of “end-goal” – i.e. deliver a high quality design by verifying it thoroughly.

 

During our regular UVM and SVA training sessions (www.cvcblr.com/trainings) we often hear few myths and we clarify them as much as we can to our attendees. Now we thought why not extend that clarity and open up that discussion for a wider audience, even those non-paying customers across the world? (We consider them to be little unfortunate not to be able to discuss these face-to-face, better luck next time!)

 

Here are some of those myths:

  • SVAs can’t be used with UVM env
  • SVAs are not for verification engineers
  • UVM – Way too complex for simple stuff
  • UVM – not for RTL designers/simple SV-Testbench folks
  • UVM & SVA don’t go hand-in-hand in same team/project/env
Do you buy into these? Please do comment here. We will show our responses in follow-up posts, so stay tuned!
TeamCVC

 

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