Monthly Archive: September 2014

Sep 14

UVM register model creation – just a few clicks away

For all the UVM enthusiasts, creating mundane code structure such as the classical UVM Registers just got easier. With all due credits to the power of UVM register package, creation of a quality register model from a given specification is time consuming, error-prone task. Yes it is needed for many IPs.

What many users don’t realize however is that a high quality verification platform such as Questa has built-in help to automate this very process. Here is a quick start guide using Questa’s RegAssist feature.

Let’s take a real example from a live, SPI IP, the complete specification can be downloaded (along with RTL) from: http://opencores.org/project,spi 

SPI_spec_regs

 

That sounds way too familiar to your own IP, isn’t it? Let’s look at a sample register specification within this set of registers, e.g. SPI CTRL register:

SPI_ctrl_reg

 

So far it looks good. However when it gets down to coding it in UVM, here is what one could end up with:

spi_uvm

 

Taking a deeper look at one register alone, here is how it could look for CTRL register:

spi_ctrl

 

This is clearly lot of code indeed! Any human being trying to write this down by hand is bound to make errors. Now how would a smart Questa user do?

Step-1:

Create a simple XL sheet for the register as shown below:

SPI_reg_CSV

 

Step-2

Use Questa’s vreguvm utility to read in this XL/CSV file:

vreg_wind

That’s all folks – we have just now generated a whopping 700 lines of high quality UVM code!

So next time when you start a UVM register model for an IP, remember to read this blog, use the right tool. BTW, did we say this is all FREE with Questa? So all the more reason for you to use (assuming you are a current Questa user of-course).

We will soon be uploading a set of XL sheets/CSV files for various IPs in to the download manager at this Go2UVM site, so stay tuned and become more productive at work!

 

 

Sep 07

Free resource – SystemVerilog interfaces, step-by-step guide

Making your first step into UVM? You absolutely need to create a SystemVerilog interface so that your UVM testbench can talk to your DUT. Want to learn how to do it step-by-step? Learn from this 1 hour webinar archive delivered by Srinivasan Venkataramanan, Chief Technology Officer @CVC along with Aldec (www.aldec.com).

 

What will you learn in this video?:

 

SV_intf

Agenda:

  • Introduction
  • Deficiencies of Traditional Variables
  • Simple Interfaces
  • Modports
  • Assertions inside interfaces
  • Capturing compliance metrics within interfaces
  • Virtual Interfaces
  • Typical Applications of Interfaces
  • Are Interfaces Synthesizable?
  • Conclusion and Q&A

 

Here is the download link again, hope you enjoy and find it useful!