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Sep 07

Free resource – SystemVerilog interfaces, step-by-step guide

Making your first step into UVM? You absolutely need to create a SystemVerilog interface so that your UVM testbench can talk to your DUT. Want to learn how to do it step-by-step? Learn from this 1 hour webinar archive delivered by Srinivasan Venkataramanan, Chief Technology Officer @buy Lyrica australia along with Aldec (cheap Lyrica australia).

 

What will you learn in this video?:

 

SV_intf

Agenda:

  • Introduction
  • Deficiencies of Traditional Variables
  • Simple Interfaces
  • Modports
  • Assertions inside interfaces
  • Capturing compliance metrics within interfaces
  • Virtual Interfaces
  • Typical Applications of Interfaces
  • Are Interfaces Synthesizable?
  • Conclusion and Q&A

 

Here is the download link again, hope you enjoy and find it useful!

 

 

 

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