Monthly Archive: November 2014

Nov 27

UVM Command Line processor example

Recently a UVM user asked how to use UVM Command line processor in a forum (See: http://goo.gl/MucwmL) . Since we posted an answer, we also ended up creating an example. Here it is for others to benefit as well:

 

[code]

// Copyright CVC www.cvcblr.com
// UVM Command line example
// Run sim as:
// vsim +field_val1=11 +uvm_set_config_int=*,ex_int,256

import uvm_pkg::*;
`include “uvm_macros.svh”

class my_test extends uvm_test;
string seq_field_val_as_str;
int seq_val_int;
int ex_int, get_res;

`uvm_component_utils (my_test)

function new (string name, uvm_component parent);
super.new (name, parent);
endfunction : new

task main_phase (uvm_phase phase);
void'(uvm_cmdline_proc.get_arg_value(“+field_val1=”,seq_field_val_as_str));
seq_val_int = seq_field_val_as_str.atoi();
`uvm_info (“CVC”, $sformatf (“String Value from cmd line is: %0s Int value is: %0d”,

seq_field_val_as_str, seq_val_int), UVM_MEDIUM)

ex_int = 22;
get_res = uvm_config_db#(uvm_bitstream_t)::get (null, “”, “ex_int”, ex_int);

`uvm_info (“CVC”, $sformatf (“get_res: %0d Int val from +uvm_set_config_int is: %0d”,

get_res, ex_int), UVM_MEDIUM)

endtask : main_phase

endclass : my_test

module m;
initial begin : b1
run_test(“my_test”);
end : b1
endmodule : m

[/code]

 

Nov 20

SystemVerilog-UVM, Verification “Hackathon”

SystemVerilog-UVM, Verification “Hackathon”

Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?

VerifLabs, www.veriflabs.com, a new venture from CVC (www.cvcblr.com) is pleased to announce “SystemVerilog-UVM, Verification Hackathon”. As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.

When: 22-Nov-2014, Saturday,10.00 AM onwards (till evening) @ CVC, Bengaluru

Register at: http://goo.gl/forms/j9yk8U30bT

Address: http://www.cvcblr.com/about_us

Cost:  FREE

Bumper prize: 1 successful and lucky winner of the contest will stand  chance to win the best selling SVA book, see: http://verifnews.org/publications/books/, subject to terms & conditions.

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/j9yk8U30bT

Agenda:

• Introduction

• Problem statement (Few designs, specifications along with RTL)

• Choose the design that suits your interest, skill level

• Code-it, “hack-it” – find those “Design errors/bugs” lurking around the “Encrypted RTL”

• Live Q&A with Srini, our CTO and UVM guru

Schedule:

• Date: 22-Nov-2014, Saturday

• Time: 10.00 AM to 5.00 PM

• Venue: CVC, Bengaluru

• Address: http://www.cvcblr.com/about_us

Directions:

Coming from BTM/Silkboard towards Marathalli.

• Hit Agara circle bus stop

• Take next right turn – that’s 27th Main

Coming from Marathalli.

• Take outer ring road towards Silkboard.

• At Agara junction, turn left to 27th Main

On 27th Main:

• On 27th main there is a petrol bunk on right side. Continue on the same road

• On your left is ICICI Bank

• LIBERTY showroom and then a

• SANGEETHA Mobile outlet

• CVC is in 2nd floor, above Sangeetha outlet

• 1st floor is CLEOS beauty Parlor.

Register via: http://goo.gl/forms/j9yk8U30bT

Nov 17

Sorting Associative Array by contents in SystemVerilog

During our ongoing SystemVerilog training at CVC (www.cvcblr.com) a smart attendee asked what happens when I sort an Associative Array. While PHP and few other language allow this through built-in functions, SV doesn’t allow it, given the complexities of ordering with respect to keys, non sortable values etc. Here is a quick example of how this can be worked around in simple int associative array (assuming we need value based sorting and maintaining the keys).

 

Nice example for a training indeed!

 

SV_AA

Nov 13

Free, hands-on, high quality SystemVerilog training “SV-lite: SVA”

Free, hands-on, high quality SystemVerilog training “SV-lite: SVA”

VerifLabs, www.veriflabs.com, a new venture from CVC (www.cvcblr.com) is pleased to announce a “Free, hands-on, high quality SystemVerilog training SV-lite: SVA”. As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.

When: 16-Nov-2014, Sunday,10.00 AM to 1.00 PM @ CVC, Bengaluru

Register at: http://goo.gl/forms/3m3qHDgFnj

Address: http://www.cvcblr.com/about_us

Cost:  FREE

Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/3m3qHDgFnj

Agenda:

  • Introduction
  • Role of SystemVerilog Assertions
  • SystemVerilog vs. Verilog
  • SystemVerilog Assertions (SVA) syntax
    • Assert, Cover, Assume
    • Property
    • Sequence
    • System Functions

Hands-on lab session:

  • Project specification
  • Pre-requisites
  • Task description (What  VerifLabs will provide)
  • Deliverables expected (Assertion code)
  • Assertion Plan discussion
  • Code, compile, simulate and verify

Schedule: 

Directions:

Coming from BTM/Silkboard towards Marathalli.

• Hit Agara circle bus stop

• Take next right turn – that’s 27th Main

Coming from Marathalli.

• Take outer ring road towards Silkboard.

• At Agara junction, turn left to 27th Main

On 27th Main:

• On 27th main there is a petrol bunk on right side. Continue on the same road

• On your left is ICICI Bank

• LIBERTY showroom and then a

• SANGEETHA Mobile outlet

• CVC is in 2nd floor, above Sangeetha outlet

• 1st floor is CLEOS beauty Parlor.

Register via: http://goo.gl/forms/3m3qHDgFnj