Nov 20

SystemVerilog-UVM, Verification “Hackathon”

SystemVerilog-UVM, Verification “Hackathon”

Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?

VerifLabs, www.veriflabs.com, a new venture from CVC (www.cvcblr.com) is pleased to announce “SystemVerilog-UVM, Verification Hackathon”. As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.

When: 22-Nov-2014, Saturday,10.00 AM onwards (till evening) @ CVC, Bengaluru

Register at: http://goo.gl/forms/j9yk8U30bT

Address: http://www.cvcblr.com/about_us

Cost:  FREE

Bumper prize: 1 successful and lucky winner of the contest will stand  chance to win the best selling SVA book, see: http://verifnews.org/publications/books/, subject to terms & conditions.

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/j9yk8U30bT


• Introduction

• Problem statement (Few designs, specifications along with RTL)

• Choose the design that suits your interest, skill level

• Code-it, “hack-it” – find those “Design errors/bugs” lurking around the “Encrypted RTL”

• Live Q&A with Srini, our CTO and UVM guru


• Date: 22-Nov-2014, Saturday

• Time: 10.00 AM to 5.00 PM

• Venue: CVC, Bengaluru

• Address: http://www.cvcblr.com/about_us


Coming from BTM/Silkboard towards Marathalli.

• Hit Agara circle bus stop

• Take next right turn – that’s 27th Main

Coming from Marathalli.

• Take outer ring road towards Silkboard.

• At Agara junction, turn left to 27th Main

On 27th Main:

• On 27th main there is a petrol bunk on right side. Continue on the same road

• On your left is ICICI Bank

• LIBERTY showroom and then a

• SANGEETHA Mobile outlet

• CVC is in 2nd floor, above Sangeetha outlet

• 1st floor is CLEOS beauty Parlor.

Register via: http://goo.gl/forms/j9yk8U30bT

2 pings

  1. SystemVerilog-UVM, Verification “Hackathon” » GO 2 UVM – for VLSI Designers | Verification News Portal - ASIC & FPGA

    […] via SystemVerilog-UVM, Verification “Hackathon” » GO 2 UVM – for VLSI Designers. […]

  2. Our UVM Hackathon – technologies & methodology behind the event | VLSI Design-Verification Labs

    […] makes this event such a challenge. If you didn’t guess it yet, yes, we are talking about the world’s first ever UVM Hackathon that is about to start in less than 12 hours from […]

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