Monthly Archive: December 2014

Dec 27

Free-UVM-training-CVC-at-10: Go2UVM – Hands-on session

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SystemVerilog, Training, Uncategorized, UVM, UVM1.2

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Free-UVM-training-CVC-at-10: Go2UVM Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 30 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register at: http://goo.gl/forms/39mWKsRbHY

Do you share any of the following concerns about UVM?

  • I know SystemVerilog and use it for TBs, but UVM is too complicated I feel
  • Is there a simple way to get started with UVM without having to go through 5-days (or more) training?
  • My Testbenches are really small and simple and UVM is way too complex for me
  • I develop traces to test my SVA (assertion) models, UVM is too complex, is it still “Universal” BTW?
  • I design & verify DSPs, UVM infrastructure sounds like overkill to me

Many of our customer do ask us the above. This is where CVC has put in deep OOP skills to assist and developed a simple Go2UVM package.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/39mWKsRbHY

Agenda:

  • Registration
  • Speaker introduction
  • Presentation
  • Networking with high-tea
  • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/39mWKsRbHY

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Dec 27

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

Categories:

SVA, SystemVerilog, Training, UVM, UVM1.2

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Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 29 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register at: http://goo.gl/forms/YkQoslRECj

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog and UVM. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space.

Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC’s VSV course as a wise step towards the same.

However when it comes to the production use, plain System Verilog falls behind in certain key areas.

Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is, technical attempt to challenge a solid DV engineer with decent SV skills.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/YkQoslRECj

Agenda:

  • • Registration
  • • Speaker introduction
  • • Presentation
  • • Networking with high-tea
  • • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/YkQoslRECj

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Dec 18

10 days of FREE UVM training + labs, our gift to the DV community

Categories:

SystemVerilog, Training, UVM, UVM1.2

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Today we had our free UVM-reg training as announced at CVC office (http://www.go2uvm.org/2014/12/free-uvm-training-labs-uvm-registers-ral-learn-to-automate/) Encouraged by the strong user interest we are keep the momentum up and going.

Also, CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested. 

No strings attached, except for the “first-come-first-serve” basis. Grab your seats ASAP by registering online. Registrations will open shortly.

To make things even more interesting, we will do “Selected Topics in UVM” every day, will keep enough variety so that users will benefit the most.

Topics to be finalized shortly, but here is a preview. Incase you have suggestions, requests, send them across to career@cvcblr.com 

  • UVM_CMD line processor

  • config-DB

    Factory

    UVM sequences

    Transaction modelling – transaction vs. seq_item vs. sequence

    Objection mechanism

    Block to sub-system reuse case study

    uvm_subscriber vs. uvm_scoreboard

    analysis_port use models

  • UVM 1.2 migration
  • UVM registers

So watch this space for more details.

TeamCVC

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Dec 11

Free UVM training + labs: UVM Registers (RAL) – learn to automate

Categories:

SystemVerilog, Training, UVM

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Free UVM training + labs: UVM Registers (RAL) – learn to automate

UVM Registers is often mis-understood part of UVM. While the true potential/power of it is very high, common, ill-guided misuse has somewhat diminished its adoption in the industry. This is an attempt to demystify UVM Registers by CVC – a global UVM expert team! We will do this in parts, the first part focuses on register modelling, automating the model creation and running the created model.

When: 2 choices:

  • Weekday: 17-Dec-2014, Wednesday, 16.00 – 19.00 (4 PM to 7 PM) @ CVC, Bengaluru
  • Weekend: 21-Dec-2014, Sunday,16.00 – 19.00  (4 PM to 7 PM) @ CVC, Bengaluru

Register at: http://goo.gl/forms/XQolI1IR5R

Address: http://cvcblr.com/?page_id=2 

Cost:  FREE

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/XQolI1IR5R

Agenda:

• UVM introduction

• Capturing registers in UVM

• Using XL sheet to capture Register Specification

• Running Questa RegAssist to create register model creation

• SPI IP with registers – an IP case study

Register via: http://goo.gl/forms/XQolI1IR5R 

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