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Dec 27

Free-UVM-training-CVC-at-10: Go2UVM – Hands-on session

Free-UVM-training-CVC-at-10: Go2UVM Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 30 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register athttp://goo.gl/forms/39mWKsRbHY

Do you share any of the following concerns about UVM?

  • I know SystemVerilog and use it for TBs, but UVM is too complicated I feel
  • Is there a simple way to get started with UVM without having to go through 5-days (or more) training?
  • My Testbenches are really small and simple and UVM is way too complex for me
  • I develop traces to test my SVA (assertion) models, UVM is too complex, is it still “Universal” BTW?
  • I design & verify DSPs, UVM infrastructure sounds like overkill to me

Many of our customer do ask us the above. This is where CVC has put in deep OOP skills to assist and developed a simple Go2UVM package.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/39mWKsRbHY

Agenda:

  • Registration
  • Speaker introduction
  • Presentation
  • Networking with high-tea
  • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/39mWKsRbHY

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