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Dec 27

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 29 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register at: http://goo.gl/forms/YkQoslRECj

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog and UVM. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space.

Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC’s VSV course as a wise step towards the same.

However when it comes to the production use, plain System Verilog falls behind in certain key areas.

Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is, technical attempt to challenge a solid DV engineer with decent SV skills.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/YkQoslRECj

Agenda:

  • • Registration
  • • Speaker introduction
  • • Presentation
  • • Networking with high-tea
  • • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/YkQoslRECj

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