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Verification “Hackathon” – Verilog/SystemVerilog/UVM

Verification “Hackathon” – Verilog/SystemVerilog/UVM

Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?  buy Lyrica online ireland, a new venture from buy Lyrical dance costumes online is pleased to announce a new session of our popular “Verification Hackathon” – use Verilog/SystemVerilog/UVM.

 As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.

When: 23-Jan-2015, Friday,10.00 AM onwards (till evening)

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Cost:  FREE* if no feedback/analysis is requested. 

       Rs. 500 /– if you need feedback and analysis on how you performed (Analysis, detailed code review will be provided by our experts team)

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• Introduction

• Problem statement (Specification along with RTL)

• Code-it, “hack-it” – find those “Design errors/bugs” lurking around the “Encrypted RTL”

• Feedback, analysis for paid contestants


• Date: 23-Jan-2015, Friday

• Time: 10.00 AM to 5.00 PM

• Venue: CVC, Bengaluru

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Jan 03

Automate UVM registers for free with Questa’s Register Assistant utility

Happy New Year 2015 to all our readers. What a great way to start the new year at CVC than to come out with all guns blazing around UVM? That’s precisely what our TeamCVC has been busy during last few weeks of 2014. We offered several free, high quality UVM training sessions as part of our 10th year celebrations. As the party continues, here is a “pictorial blog” on:

“How to automate UVM register model generation?”

What’s a “pictorial blog”? – a blog entry with more pictures than TEXT 🙂

Since this is a little longer than usual blog (as it is “pictorial”), let’s make it spicy: What does 007 have to do with UVM and YOU?

james-bond-007-logo mp_007-1

Well, read on to find out:

Consider a peripheral IP such as SPI:


A sample Master implementation in RTL is available via cheap flights lyrics Below is a link to the full specification if desired.

Focusing on the register portion of the spec alone:

Delving into SPI Control Register:



Now, if you want to verify these register implementation including their access restrictions, write-read paths etc. using UVM, that can be a lot of code to write. Good news is we can automate this and that too for FREE* (For Mentor Questa users in this case).

First step would be to create a simple XL sheet with these register definitions as below:



Do you think that’s some work as well? Why not download it for free from here?

Now, what’s next? Well, let’s invoke Questa’s Register Assistant:



Then you have few options to choose the UVM version for instance:



Take a look at the generated UVM code:




Also look closely at the SPI CTRL register generated code:


Wow, that’s lot of automation for a single mouse click:mouse-click

Hold on, that’s not all, Questa does more – it builds the entire reg-model, configures each register as per the specification (ref. CSV file):



And finally it also does the “mapping” of each register:



So we are ready to GO! Let’s write a simple, dummy test as an experiment:



Note: this is part-1 of this “pictorial blog” on this topic:



Let’s take a look at the UVM run results:



So, What’s up?



As a recap – Questa’s Register Assistant is indeed your friendly “MoneyPenny” if you wish 🙂



Use the CSV file format and automate your UVM code on the go!


Have a great 2015 ahead. Do contact us via can you buy Lyrica from canada if you need a hands-on UVM session.

Here are the download links for the SPI IP: