Monthly Archive: June 2016

Jun 19

Go2UVM package 2016.05 now available

With UVM taking center stage in VLSI design verification at large, more and more new users are looking at adopting UVM. While the existing ASIC DV teams are getting more and more sophisticated with their UVM flow, Go2UVM.org serves as the GO-TO site for advanced use cases, debug flows etc. Specifically we have released 2 UVM tit-bit articles for advanced UVM users at:

  1. Debug UVM factory with these great tips!
  2. UVM tit-bit – m_sequencer vs. p_sequencer

At the other end of spectrum of potential UVM users are the students, educational institutions and smaller FPGA teams that do not have the resources (and sometime the necessity as well) to adopt UVM in its full capacity to begin with. Our Open-Source Go2UVM package serves this segment by enabling them to get started with UVM with minimal investment. While Go2UVM package has been in production for a few quarters now, the latest version 2016.05 has added examples for Cadence’s IUS simulator on top of existing Mentor and Aldec tool support. The main drive behind adding CDN support came from a recent DVTalk event held at BMS College of Engineering where-in some 40+ Master graduate students tried their first ever UVM coding recently.

Download the latest Go2UVM package 2016.05 from the link below:

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Here is a whitepaper on Go2UVM motivation and use models.[wpfilebase tag=file id=8 /]

And if you are part of an academic institution and want to schedule a 1-day free UVM training at your premises, see: Free Go2UVM training

In the next release we are adding “apps” to generate Go2UVM skeleton for various EDA tools, so stay tuned!

Jun 11

Debug UVM factory with these great tips!

We recently wrote an article for Mentor Graphics’s popular Verification Horizons magazine, June 2016 | Volume 12, Issue 2

Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best practices.

Given the major adoption of UVM across the globe and across the industry, advanced users are looking for tips and tricks to improve their productivity. UVM does define a structured framework for building complex testbenches. It is built on strong OOP principles and design patterns using underlying SystemVerilog language features. This strong OOP nature presents certain challenges to the end users. Recall that many Design-Verification (DV) engineers come from hardware, electronics backgrounds and not heavy Software backgrounds. Hence at times it gets tricky for users to debug UVM based testbenches when things do not work as expected.

In this article the authors share their long experience of assisting customers with run time debug of common UVM issues and potential solutions to them. During our various training and consulting engagements using UVM we have seen DV engineers struggling to debug relatively simple UVM issues. It will be unfair to blame the users as many a times, the error messages are cryptic and do not point to the actual source code, rather somewhere from the base classes, making the debug difficult. We have captured a series of such common issues and error messages into a collateral form that we call “UVM Vault”. As part of our QVP engagement with Mentor Graphics, we are integrating this UVM Vault to Questa® in the near future.

Download the UVM Debug techniques as PDF below:

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You can read full Horizons article at: https://verificationacademy.com/verification-horizons/june-2016-volume-12-issue-2

Jun 09

UVM tit-bit – m_sequencer vs. p_sequencer

Often we see users asking: what are the 2 sequencer pointers – m_sequencer vs. p_sequencer ?

Having trained 1000s of engineers in this domain, CVC (http://www.cvcblr.com) is glad to release attached PDF for free users to appreciate this key feature. So go ahead enjoy reading the same!

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