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Jun 19

Go2UVM package 2016.05 now available

With UVM taking center stage in VLSI design verification at large, more and more new users are looking at adopting UVM. While the existing ASIC DV teams are getting more and more sophisticated with their UVM flow, Go2UVM.org serves as the GO-TO site for advanced use cases, debug flows etc. Specifically we have released 2 UVM tit-bit articles for advanced UVM users at:

  1. Debug UVM factory with these great tips!
  2. UVM tit-bit – m_sequencer vs. p_sequencer

At the other end of spectrum of potential UVM users are the students, educational institutions and smaller FPGA teams that do not have the resources (and sometime the necessity as well) to adopt UVM in its full capacity to begin with. Our Open-Source Go2UVM package serves this segment by enabling them to get started with UVM with minimal investment. While Go2UVM package has been in production for a few quarters now, the latest version 2016.05 has added examples for Cadence’s IUS simulator on top of existing Mentor and Aldec tool support. The main drive behind adding CDN support came from a recent DVTalk event held at BMS College of Engineering where-in some 40+ Master graduate students tried their first ever UVM coding recently.

Download the latest Go2UVM package 2016.05 from the link below:

VW Go2UVM Pkg 2016.05 Tar
VW Go2UVM Pkg 2016.05 Tar
VW_Go2UVM_Pkg_2016.05.tar.gz
1.9 MiB
60 Downloads
Details

Here is a whitepaper on Go2UVM motivation and use models.

White Paper Go2UVM For Non OOP Users
White Paper Go2UVM For Non OOP Users » Post
White_paper_Go2UVM_for_non_OOP_users.pdf
557.4 KiB
115 Downloads
Details

And if you are part of an academic institution and want to schedule a 1-day free UVM training at your premises, see: Free Go2UVM training

In the next release we are adding “apps” to generate Go2UVM skeleton for various EDA tools, so stay tuned!

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