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Jul 20

Advanced UVM tutorial (from DVCon US 2016) slides now available

As we promote UVM from basics to advanced user base across the globe, we are glad to share our UVM tutorial slides covering advanced topics. This tutorial was presented at recent DVCon USA 2016 along with Synopsys and others. Referring to the event summary at: http://events.dvcon.org/events/proceedings.aspx?id=199-1-T 

Debugging UVM testbenches can be extremely difficult because errors often appear in lines of SystemVerilog code that make up the UVM package, as opposed to the user written code. Most of these errors can easily be eliminated by following a structured approach to debugging that targets these common errors first. This part of the tutorial will walk through run-time errors and built in debugging features in UVM and how to use them.

You can download the PDF from here for free:

VerifWorks's UVM Tutorial at DVCon USA 2016
VerifWorks's UVM Tutorial at DVCon USA 2016
VW_UVM_tutorial_DVCon_US_2016.pdf
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