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Handling variable delays in SystemVerilog Assertions

Have you got a modern design that has dynamic, variable latency bet’n request and response? Do you want to model that behavior in your verification code using SystemVerilog? Assertions are great way to capture such temporal requirements and verify them in simulations.

A more formal requirement
// After “start_sig” goes high
// within a variable delay of “var_del” clock cycles
// signal “end_sig” should go high

A first-cut SVA implementaion would look like below:

start_sig |-> ##[1:var_del] end_sig

However SVA as in IEEE 1800-2012 does NOT allow variable delays in properties/sequences. That would mean that assuming the var_del is a variable (int/integer/logic vector etc.) the above code won’t compile 🙁

 A work-around is to use local variable and count.

The core code is below:

sva_var_del

So what’s happening?

Line-3: Once you see a HIGH on start_sig, save the current value of var_del (Remember it is a variable, could change during the course of checking this transfer) in a local variable (v_cnt)

Line-4: Start decrementing v_cnt value once per clock (Till.. see next line)

Line-5: As soon as you see end_sig make sure your transfer did NOT timeout/expire

For all FSM lovers, here is the logic as a bubble diagram:

sva_var_del_fsm-png

In this example we have implemented that logic inside a “checker” (a new construct in SV) and make it easy for end users.

Now how do we “verify” this logic? Well, let’s use UVM trace with Go2UVM. One of the key benefits of Go2UVM is that while testing an assertion/checker for proper functionality, one could predict the errors and report them with SVUnit’s report-mock feature.

See go2uvm_tb_src/vw_var_del_in_sva_uvm.sv and look for expect_error API usage. We use that prediction for an intended fail trace and in the log file you will see the test still passes (as expected) despite the presence of an UVM_ERROR (again note that the test intentionally introduces errors and expects the SVA to flag it appropriately).

You can download the fully ready code as a tar ball below:

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vw_var_del_in_sva.tgz
3.6 KiB
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Files Description:

UVM Trace –> go2uvm_tb_src/vw_var_del_in_sva_uvm.sv
SVA code –> sva_src/vw_var_del_in_sva.sv

To run;

cd run_dir
make cvc2 (for Questa). Other targets are available for other tools as we use a generic Makefile from: buy Lyrica online australia