Feb 27

Register testing made simple – Go2UVM app!

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Feb 14

Waves2UVM – a Go2UVM app

For long, engineers needed an easy and scalable way to capture timing diagrams as part of their design specifications. There have been few commercial tools to help in this task. A relatively new tool named WaveDrom has been developed as an open-source JSON based solution for this. Quoting WaveDrom.com site: WaveDrom draws your Timing Diagram or …

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Feb 03

Simplifying UVM messaging – `g2u_display()

As part of our goal to making UVM easy-to-use, we keep adding more features to the Go2UVM library. One of the recent additions is “Simplified messaging in UVM”. Intention is to bring the benefits of UVM messaging to all Verilog-aware engineers in the easiest way. Looking back at Verilog’s native $display(), it is the most used debug …

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Dec 07

UVM Registers – first step to Portable Stimulus, free training

For those using UVM in live projects and looking to see what’s next in DV – here is an opportunity to learn (for free) UVM Registers -a definitive first step to “Portable Stimulus”. Accellera’s PSS working group is working on defining how a portable test specification can be defined and is expected to be the next …

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Nov 11

Handling variable delays in SystemVerilog Assertions

Have you got a modern design that has dynamic, variable latency bet’n request and response? Do you want to model that behavior in your verification code using SystemVerilog? Assertions are great way to capture such temporal requirements and verify them in simulations. A more formal requirement // After “start_sig” goes high // within a variable …

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Oct 27

Generic Makefile for UVM simulations

Given the widespread usage of UVM across the globe, many first timers to UVM find it hard to remember all relevant options to their favourite simulator to get going with UVM. Our Go2UVM approach is addressing this very issue via a generic Makefile. Given most of the VLSI engineers are familiar with Makefile use model, …

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