About Us

UVM – Universal Verification Methodology is THE standard for creating reusable, structured verification environment for modern day electronics designs (both ASICs & FPGAs). It is the mainstream design verification methodology for integrated circuits (ICs in VLSI domain).

It is developed by various semiconductor design companies and EDA vendors and is available for FREE to anyone, see:  http://www.accellera.org/activities/committees/uvm

GO-2-UVM is intended to be the GOTO site for users of this powerful methodology across the world encompassing various user base such as team leads, managers, engineers, students and research scholars.

This initiative is yet another way CVC (www.cvcblr.com) attempts to serve the VLSI ecosystem. Being led by team of recognized SystemVerilog, SVA and UVM experts, we strongly believe there is a need for a free support desk for this vast, fascinating Universal Verification Methodology.

 

Go ahead and sign up at our discussion forums, ask those questions you always wanted to ask, but didn’t know whom to ask, and get peers, experts responses – all for free!

Warm Regards

TeamCVC  (Srini, Ajeetha and others in our Dynamic TeamCVC)

2 comments

  1. Karthik

    It is a good initiative. Looking forward good discussions and knowledge sharing.

  2. Subhash

    Hello

    Can you help me understand what is uvm_lite all about?

    i suppose it is not a new library all together except for some additional features to the existing UVM1.1/1.2?

    Is uvm_lite a learning tool, am not too sure about this.

    Can anyone help me here?

    -Best Regards
    Subhash

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