Category Archive: EDA

Feb 27

Register testing made simple – Go2UVM app!

Go2UVM has a major update on the eve of DVCon USA 2017. We added several new features including:

  • Simplified messaging via new macros
  • Support for arbitrary signal access to enable force/deposit/release on DUT signals
  • Waves2UVM – a handy way to convert timing diagrams to UVM tests
  • Register layer app – the BIG one!

While UVM Register layer has been around for few years, an average UVM-aware engineer finds it hard to adopt quickly (compared to rest of UVM). This gets even more tough for RTL Designers looking to do some quick sanity tests on their RTL before handing it off to full-fledged DV teams. As part of our mission to “Go to UVM – the fastest way”, we have added a new app to assist in this process.

Generating UVM registers from an IP-XACT/SystemRDL/XML/YAML files has been around for many years. A limited edition of this capability exists as part of VerifWorks’s DVCreate-PSS tool as well.

However using the UVM register model to create quality tests requires more work form the user side. Part of the problem is to do with the various DUT protocols used to configure the registers as part of the designs. Go2uVM’s new register app targets exactly this problem, i.e. it builds on top of a generated UVM register model and makes it a push-button solution for simple designs to use register layer. When deployed correctly, this can lead to productive results in less than 30 minutes flat for an average RTL Designer (enabling him/her with many UVM capabilities). So how does it work? Below are the pieces needed to perform early register testing for a new RTL.

  • Register spec (IP-XACT and the likes)
  • Protocol specification to write and read from the registers
  • Some use case scenarios

A first step would be to create a UVM register model from the IP-XACT through available tools. The second step involves writing a small BFM (Bus Functional Model) to capture bus write-read protocol. With Go2UVM’s latest register app, we pushed this to a SystemVerilog interface named g2u_reg_if. A skeleton code looks as below:

interface g2u_reg_if (input logic clk);

// Relevant signal declarations

task g2u_write (uvm_reg_addr_t wr_addr, uvm_reg_data_t wr_data);

// Actual protocol to write to RTL
endtask : g2u_write

task g2u_read (uvm_reg_addr_t rd_addr, output uvm_reg_data_t rd_data);
// Actual protocol to read from RTL

endtask : g2u_read

endinterface : g2u_reg_if

 

Once a basic BFM inside a g2u_reg_if is created, our latest app does the remaining work and creates a thin UVM environment with:

  • Register model instance, creation & build
  • Built-in Go2UVM register agent (g2u_reg_agent) instance and connections
  • Necessary UVM register adaptors (bus2reg() and reg2bus())
  • A thin UVM driver-sequencer-agent-monitor hierarchy

For any new design with a different protocol, only the interface requires updates.Typical tests that are readily available with Go2UVM app includes:

  • Hardware reset and post reset value checking
  • Bit-bashing of all registers and fields (as defined in the IP-XACT spec for the given design)
  • Register access policy checks
  • Aliasing tests (On need basis)

A typical test using the Go2uMV register app looks like below:

We will soon be adding more examples including sample designs from OpenCores, typical protocols such as AHB-Lite, AXI, WishBone etc. to our GitHub repository. Meanwhile the latest release of Go2UVM is 2017.01 and is available under LGPL license from the link below:

Go2UVM on GitHub

We will be showing this in detail at DVCon USA 2017 as part of a UVM tutorial as well.

Let’s Go-to-UVM!

 

Feb 14

Waves2UVM – a Go2UVM app

For long, engineers needed an easy and scalable way to capture timing diagrams as part of their design specifications. There have been few commercial tools to help in this task. A relatively new tool named WaveDrom has been developed as an open-source JSON based solution for this. Quoting WaveDrom.com site:

WaveDrom draws your Timing Diagram or Waveform from simple textual description.
It comes with description language, rendering engine and the editor.
WaveDrom editor works in the browser or can be installed on your system.
Rendering engine can be embeded into any webpage.

So essentially when you are creating a new design specification and want to capture the timing relationship as a waveform, this utility can be very handy. For instance, below is a screenshot of ARM APB 2.0 specification (for Figure 3-4 in ARM specification):

The above diagram is very easy to create using JSON like syntax with WaveDrom editor – we will offer a download of the JSON file soon here for APB 2.0 specification. For many seasoned digital designers, a diagram such as above is a great source of reference to create:

  • Stimulus (i.e. apply the signal transitions as found in the specification to DUT – Design Under Test)
  • Checks – assertions in the form of SystemVerilog Assertions (SVA) for instance.

As part of our mission to widen UVM adoption across teams, we developed a tiny “app” that reads WaveDrom file and creates a UVM Test through Go2UVM Test API. With this app (Soon to be released along with latest Go2UVM 2017.01 release), one can input this waves.wd file and get a SystemVerilog-UVM test that can be run on a compliant DUT (RTL model for instance). The usage is quite straightforward:

perl $VW_GO2UVM_HOME/bin/vw_dvc_wd_apps.pl

The above app creates the following infrastructure necessary to reproduce the same timing diagram in a typical UVM simulation:

  • SystemVerilog interface file
  • Go2UVM Test that toggles wires as per the specification in the WaveDrom file
  • Top file that instantiates the test, connects the interface etc.
  • Makefile to run on all popular EDA tools.

 

Some of the screenshots from the app when ran on an APB 2.0 waves is below:

 

Go2UVM Test:

So as we are about to roll-out our latest Go2UVM library 2017.01 during DVCon USA 2017, there is a lot to look forward to! Stay tuned for more updates.

 

 

 

Dec 07

UVM Registers – first step to Portable Stimulus, free training

For those using UVM in live projects and looking to see what’s next in DV – here is an opportunity to learn (for free) UVM Registers -a definitive first step to “Portable Stimulus”. Accellera’s PSS working group is working on defining how a portable test specification can be defined and is expected to be the next big wave in DV space.

CVC, a global leader in VLSI Design-Verification training is pleased to offer a free half-a-day training on UVM RAL/Registers. It is free of cost, but registration is must.

Register at: https://goo.gl/forms/2UQvmI90Lp6dgKwk2

When? Dec 17th, 2016 Saturday, 10 AM – 1 PM (Indian Standard Time)

Address: http://www.fb.com/cvc.uvm/about 

Cost:  FREE

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis.

Agenda:

• UVM introduction

• Capturing registers in UVM

• Using XL sheet to capture Register Specification

• Brief look at IP-XACT for register specification

• Case studies: popular IPs and their register specifications

• Demo: VerifWorks DVCreate PSS tool to generate UVM-RAL model from IP-XACT

Register via: https://goo.gl/forms/2UQvmI90Lp6dgKwk2

 

 

 

Oct 27

Generic Makefile for UVM simulations

Given the widespread usage of UVM across the globe, many first timers to UVM find it hard to remember all relevant options to their favourite simulator to get going with UVM. Our Go2UVM approach is addressing this very issue via a generic Makefile. Given most of the VLSI engineers are familiar with Makefile use model, we provide a free to use (even for commercial deployment) Makefile here:

Makefile for compiling and running any UVM simulation with any EDA tool
2.4 KiB
81 Downloads
Details

So how does this work?

  1. Create a text file named “flist” that contains names (and paths as necessary) of all the design and Testbench files.
  2. Choose your favourite simulator – Synopsys, Cadence, Mentor or Aldec – we support all of them in single Makefile.
  3. On a terminal type: make cvc2_gui TOP=my_chip_uvm_tb_top TEST=my_uvm_test

That’s it!

Here are different EDA tool supported along with our Makefile target names:

go2uvm_makefile_targets

 

 

Jun 19

Go2UVM package 2016.05 now available

With UVM taking center stage in VLSI design verification at large, more and more new users are looking at adopting UVM. While the existing ASIC DV teams are getting more and more sophisticated with their UVM flow, Go2UVM.org serves as the GO-TO site for advanced use cases, debug flows etc. Specifically we have released 2 UVM tit-bit articles for advanced UVM users at:

  1. Debug UVM factory with these great tips!
  2. UVM tit-bit – m_sequencer vs. p_sequencer

At the other end of spectrum of potential UVM users are the students, educational institutions and smaller FPGA teams that do not have the resources (and sometime the necessity as well) to adopt UVM in its full capacity to begin with. Our Open-Source Go2UVM package serves this segment by enabling them to get started with UVM with minimal investment. While Go2UVM package has been in production for a few quarters now, the latest version 2016.05 has added examples for Cadence’s IUS simulator on top of existing Mentor and Aldec tool support. The main drive behind adding CDN support came from a recent DVTalk event held at BMS College of Engineering where-in some 40+ Master graduate students tried their first ever UVM coding recently.

Download the latest Go2UVM package 2016.05 from the link below:

VW Go2UVM Pkg 2016.05 Tar
VW Go2UVM Pkg 2016.05 Tar
VW_Go2UVM_Pkg_2016.05.tar.gz
1.9 MiB
60 Downloads
Details

Here is a whitepaper on Go2UVM motivation and use models.

White Paper Go2UVM For Non OOP Users
White Paper Go2UVM For Non OOP Users » Post
White_paper_Go2UVM_for_non_OOP_users.pdf
557.4 KiB
115 Downloads
Details

And if you are part of an academic institution and want to schedule a 1-day free UVM training at your premises, see: Free Go2UVM training

In the next release we are adding “apps” to generate Go2UVM skeleton for various EDA tools, so stay tuned!

May 10

Behind-the-scenes view of Go2UVM package – with images

With the recent release of Go2UVM package version 2016.04 VW Go2UVM Pkg 2016.04 attracting more interest in the community, our team is glad to release some of the “behind-the-scenes” picture of how this simple-yet-convenient package works on top of standard UVM.

VW Go2UVM Pkg 2016.04
VW Go2UVM Pkg 2016.04
VW_Go2UVM_Pkg_2016.04.tar.tgz
1.9 MiB
41 Downloads
Details

These screenshots were generated using Aldec’s Riviera-PRO simulator and its various UVM specific debug features.

Showing all the classes behind the scene via Riviera’s class browser:

go2uvm_class_view_rvra

Handy, schematic view of UVM – what Aldec calls as “UVM Graph” – as you can see, we cut through all complexities and add only one layer to get started with UVM – truly let’s GO to UVM!

go2uvm_graph_view_rvra

A more powerful, UVM Toolbox view of Riviera-PRO reveals more details of this Go2UVM package:

go2uvm_toolbox_view_rvra

Last but not the least – here is the source view – stay tuned, we are adding a generator to automate this source code generation with Aldec’s Riviera-PRO shortly.

go2uvm_src_view_rvra

For more on Aldec’s UVM debug capabilities, read our partner blog @ Visualizing UVM Environments: Debug Features Deliver a Clearer View

And you can download the 2016.04 release of Go2UVM from here:

http://www.go2uvm.org/download/VW_Go2UVM_Pkg_2016.04.tar.gz 

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