Go2UVM has a major update on the eve of DVCon USA 2017. We added several new features including:

• Simplified messaging via new macros
• Support for arbitrary signal access to enable force/deposit/release on DUT signals
• Waves2UVM – a handy way to convert timing diagrams to UVM tests
• Register layer app – the BIG one!

While UVM Register layer has been around for few years, an average UVM-aware engineer finds it hard to adopt quickly (compared to rest of UVM). This gets even more tough for RTL Designers looking to do some quick sanity tests on their RTL before handing it off to full-fledged DV teams. As part of our mission to “Go to UVM – the fastest way”, we have added a new app to assist in this process.

Generating UVM registers from an IP-XACT/SystemRDL/XML/YAML files has been around for many years. A limited edition of this capability exists as part of VerifWorks’s DVCreate-PSS tool as well.

However using the UVM register model to create quality tests requires more work form the user side. Part of the problem is to do with the various DUT protocols used to configure the registers as part of the designs. Go2uVM’s new register app targets exactly this problem, i.e. it builds on top of a generated UVM register model and makes it a push-button solution for simple designs to use register layer. When deployed correctly, this can lead to productive results in less than 30 minutes flat for an average RTL Designer (enabling him/her with many UVM capabilities). So how does it work? Below are the pieces needed to perform early register testing for a new RTL.

• Register spec (IP-XACT and the likes)
• Protocol specification to write and read from the registers
• Some use case scenarios

A first step would be to create a UVM register model from the IP-XACT through available tools. The second step involves writing a small BFM (Bus Functional Model) to capture bus write-read protocol. With Go2UVM’s latest register app, we pushed this to a SystemVerilog interface named g2u_reg_if. A skeleton code looks as below:

interface g2u_reg_if (input logic clk);

// Relevant signal declarations

task g2u_write (uvm_reg_addr_t wr_addr, uvm_reg_data_t wr_data);

// Actual protocol to write to RTL
endtask : g2u_write

task g2u_read (uvm_reg_addr_t rd_addr, output uvm_reg_data_t rd_data);
// Actual protocol to read from RTL

endtask : g2u_read

endinterface : g2u_reg_if

Once a basic BFM inside a g2u_reg_if is created, our latest app does the remaining work and creates a thin UVM environment with:

• Register model instance, creation & build
• Built-in Go2UVM register agent (g2u_reg_agent) instance and connections
• Necessary UVM register adaptors (bus2reg() and reg2bus())
• A thin UVM driver-sequencer-agent-monitor hierarchy

For any new design with a different protocol, only the interface requires updates.Typical tests that are readily available with Go2UVM app includes:

• Hardware reset and post reset value checking
• Bit-bashing of all registers and fields (as defined in the IP-XACT spec for the given design)
• Register access policy checks
• Aliasing tests (On need basis)

A typical test using the Go2uMV register app looks like below:

We will soon be adding more examples including sample designs from OpenCores, typical protocols such as AHB-Lite, AXI, WishBone etc. to our GitHub repository. Meanwhile the latest release of Go2UVM is 2017.01 and is available under LGPL license from the link below:

Go2UVM on GitHub

We will be showing this in detail at DVCon USA 2017 as part of a UVM tutorial as well.

Let’s Go-to-UVM!

With UVM taking center stage in VLSI design verification at large, more and more new users are looking at adopting UVM. While the existing ASIC DV teams are getting more and more sophisticated with their UVM flow, Go2UVM.org serves as the GO-TO site for advanced use cases, debug flows etc. Specifically we have released 2 UVM tit-bit articles for advanced UVM users at:

1. Debug UVM factory with these great tips!
2. UVM tit-bit – m_sequencer vs. p_sequencer

At the other end of spectrum of potential UVM users are the students, educational institutions and smaller FPGA teams that do not have the resources (and sometime the necessity as well) to adopt UVM in its full capacity to begin with. Our Open-Source Go2UVM package serves this segment by enabling them to get started with UVM with minimal investment. While Go2UVM package has been in production for a few quarters now, the latest version 2016.05 has added examples for Cadence’s IUS simulator on top of existing Mentor and Aldec tool support. The main drive behind adding CDN support came from a recent DVTalk event held at BMS College of Engineering where-in some 40+ Master graduate students tried their first ever UVM coding recently.

Download the latest Go2UVM package 2016.05 from the link below:

[wpfilebase tag=file id=13 /]

Here is a whitepaper on Go2UVM motivation and use models.[wpfilebase tag=file id=8 /]

And if you are part of an academic institution and want to schedule a 1-day free UVM training at your premises, see: Free Go2UVM training

In the next release we are adding “apps” to generate Go2UVM skeleton for various EDA tools, so stay tuned!