Category Archive: SVA

Nov 11

Handling variable delays in SystemVerilog Assertions

Have you got a modern design that has dynamic, variable latency bet’n request and response? Do you want to model that behavior in your verification code using SystemVerilog? Assertions are great way to capture such temporal requirements and verify them in simulations.

A more formal requirement
// After “start_sig” goes high
// within a variable delay of “var_del” clock cycles
// signal “end_sig” should go high

A first-cut SVA implementaion would look like below:

start_sig |-> ##[1:var_del] end_sig

However SVA as in IEEE 1800-2012 does NOT allow variable delays in properties/sequences. That would mean that assuming the var_del is a variable (int/integer/logic vector etc.) the above code won’t compile 🙁

 A work-around is to use local variable and count.

The core code is below:

sva_var_del

So what’s happening?

Line-3: Once you see a HIGH on start_sig, save the current value of var_del (Remember it is a variable, could change during the course of checking this transfer) in a local variable (v_cnt)

Line-4: Start decrementing v_cnt value once per clock (Till.. see next line)

Line-5: As soon as you see end_sig make sure your transfer did NOT timeout/expire

For all FSM lovers, here is the logic as a bubble diagram:

sva_var_del_fsm-png

In this example we have implemented that logic inside a “checker” (a new construct in SV) and make it easy for end users.

Now how do we “verify” this logic? Well, let’s use UVM trace with Go2UVM. One of the key benefits of Go2UVM is that while testing an assertion/checker for proper functionality, one could predict the errors and report them with SVUnit’s report-mock feature.

See go2uvm_tb_src/vw_var_del_in_sva_uvm.sv and look for expect_error API usage. We use that prediction for an intended fail trace and in the log file you will see the test still passes (as expected) despite the presence of an UVM_ERROR (again note that the test intentionally introduces errors and expects the SVA to flag it appropriately).

You can download the fully ready code as a tar ball below:

[wpfilebase tag=file id=19 /]

Files Description:

UVM Trace –> go2uvm_tb_src/vw_var_del_in_sva_uvm.sv
SVA code –> sva_src/vw_var_del_in_sva.sv

To run;

cd run_dir
make cvc2 (for Questa). Other targets are available for other tools as we use a generic Makefile from: Generic Makefile for UVM

Jan 17

Verification “Hackathon” – Verilog/SystemVerilog/UVM

Verification “Hackathon” – Verilog/SystemVerilog/UVM

Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?  VerifLabs, www.veriflabs.com, a new venture from CVC (www.cvcblr.com) is pleased to announce a new session of our popular “Verification Hackathon” – use Verilog/SystemVerilog/UVM.

 As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.

When: 23-Jan-2015, Friday,10.00 AM onwards (till evening)

Where: CVC office, Bengaluru  Address: http://cvcblr.com/?page_id=2  

Register at: http://goo.gl/forms/55afc4kMbo

Cost:  FREE* if no feedback/analysis is requested. 

       Rs. 500 /– if you need feedback and analysis on how you performed (Analysis, detailed code review will be provided by our experts team)

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/   

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/55afc4kMbo

Agenda:

• Introduction

• Problem statement (Specification along with RTL)

• Code-it, “hack-it” – find those “Design errors/bugs” lurking around the “Encrypted RTL”

• Feedback, analysis for paid contestants

Schedule:

• Date: 23-Jan-2015, Friday

• Time: 10.00 AM to 5.00 PM

• Venue: CVC, Bengaluru

• Address: http://cvcblr.com/?page_id=2

Register at: http://goo.gl/forms/55afc4kMbo

==============

Directions:

Coming from BTM/Silkboard towards Marathalli.

• Hit Agara circle bus stop

• Take next right turn – that’s 27th Main

Coming from Marathalli.

• Take outer ring road towards Silkboard.

• At Agara junction, turn left to 27th Main

On 27th Main:

• On 27th main there is a petrol bunk on right side. Continue on the same road

• On your left is ICICI Bank

• LIBERTY showroom and then a

• SANGEETHA Mobile outlet

• CVC is in 2nd floor, above Sangeetha outlet

• 1st floor is CLEOS beauty Parlor.

Register at: http://goo.gl/forms/55afc4kMbo

Dec 27

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 29 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register at: http://goo.gl/forms/YkQoslRECj

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog and UVM. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space.

Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC’s VSV course as a wise step towards the same.

However when it comes to the production use, plain System Verilog falls behind in certain key areas.

Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is, technical attempt to challenge a solid DV engineer with decent SV skills.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/YkQoslRECj

Agenda:

  • • Registration
  • • Speaker introduction
  • • Presentation
  • • Networking with high-tea
  • • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/YkQoslRECj

Nov 13

Free, hands-on, high quality SystemVerilog training “SV-lite: SVA”

Free, hands-on, high quality SystemVerilog training “SV-lite: SVA”

VerifLabs, www.veriflabs.com, a new venture from CVC (www.cvcblr.com) is pleased to announce a “Free, hands-on, high quality SystemVerilog training SV-lite: SVA”. As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.

When: 16-Nov-2014, Sunday,10.00 AM to 1.00 PM @ CVC, Bengaluru

Register at: http://goo.gl/forms/3m3qHDgFnj

Address: http://www.cvcblr.com/about_us

Cost:  FREE

Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/3m3qHDgFnj

Agenda:

  • Introduction
  • Role of SystemVerilog Assertions
  • SystemVerilog vs. Verilog
  • SystemVerilog Assertions (SVA) syntax
    • Assert, Cover, Assume
    • Property
    • Sequence
    • System Functions

Hands-on lab session:

  • Project specification
  • Pre-requisites
  • Task description (What  VerifLabs will provide)
  • Deliverables expected (Assertion code)
  • Assertion Plan discussion
  • Code, compile, simulate and verify

Schedule: 

Directions:

Coming from BTM/Silkboard towards Marathalli.

• Hit Agara circle bus stop

• Take next right turn – that’s 27th Main

Coming from Marathalli.

• Take outer ring road towards Silkboard.

• At Agara junction, turn left to 27th Main

On 27th Main:

• On 27th main there is a petrol bunk on right side. Continue on the same road

• On your left is ICICI Bank

• LIBERTY showroom and then a

• SANGEETHA Mobile outlet

• CVC is in 2nd floor, above Sangeetha outlet

• 1st floor is CLEOS beauty Parlor.

Register via: http://goo.gl/forms/3m3qHDgFnj