Category Archive: Training

Dec 07

UVM Registers – first step to Portable Stimulus, free training

For those using UVM in live projects and looking to see what’s next in DV – here is an opportunity to learn (for free) UVM Registers -a definitive first step to “Portable Stimulus”. Accellera’s PSS working group is working on defining how a portable test specification can be defined and is expected to be the next big wave in DV space.

CVC, a global leader in VLSI Design-Verification training is pleased to offer a free half-a-day training on UVM RAL/Registers. It is free of cost, but registration is must.

Register at: https://goo.gl/forms/2UQvmI90Lp6dgKwk2

When? Dec 17th, 2016 Saturday, 10 AM – 1 PM (Indian Standard Time)

Address: http://www.fb.com/cvc.uvm/about 

Cost:  FREE

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis.

Agenda:

• UVM introduction

• Capturing registers in UVM

• Using XL sheet to capture Register Specification

• Brief look at IP-XACT for register specification

• Case studies: popular IPs and their register specifications

• Demo: VerifWorks DVCreate PSS tool to generate UVM-RAL model from IP-XACT

Register via: https://goo.gl/forms/2UQvmI90Lp6dgKwk2

 

 

 

Jul 20

Advanced UVM tutorial (from DVCon US 2016) slides now available

As we promote UVM from basics to advanced user base across the globe, we are glad to share our UVM tutorial slides covering advanced topics. This tutorial was presented at recent DVCon USA 2016 along with Synopsys and others. Referring to the event summary at: http://events.dvcon.org/events/proceedings.aspx?id=199-1-T 

Debugging UVM testbenches can be extremely difficult because errors often appear in lines of SystemVerilog code that make up the UVM package, as opposed to the user written code. Most of these errors can easily be eliminated by following a structured approach to debugging that targets these common errors first. This part of the tutorial will walk through run-time errors and built in debugging features in UVM and how to use them.

You can download the PDF from here for free:

VerifWorks's UVM Tutorial at DVCon USA 2016
VerifWorks's UVM Tutorial at DVCon USA 2016
VW_UVM_tutorial_DVCon_US_2016.pdf
3.5 MiB
204 Downloads
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Jun 09

UVM tit-bit – m_sequencer vs. p_sequencer

Often we see users asking: what are the 2 sequencer pointers – m_sequencer vs. p_sequencer ?

Having trained 1000s of engineers in this domain, CVC (http://www.cvcblr.com) is glad to release attached PDF for free users to appreciate this key feature. So go ahead enjoy reading the same!

UVM m_sequencer vs. p_sequencer
UVM m_sequencer vs. p_sequencer
CVC_m_sequencer_vs_p_sequencer.pdf
Version: 1.0
957.4 KiB
167 Downloads
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Jan 03

Automate UVM registers for free with Questa’s Register Assistant utility

Happy New Year 2015 to all our readers. What a great way to start the new year at CVC than to come out with all guns blazing around UVM? That’s precisely what our TeamCVC has been busy during last few weeks of 2014. We offered several free, high quality UVM training sessions as part of our 10th year celebrations. As the party continues, here is a “pictorial blog” on:

“How to automate UVM register model generation?”

What’s a “pictorial blog”? – a blog entry with more pictures than TEXT 🙂

Since this is a little longer than usual blog (as it is “pictorial”), let’s make it spicy: What does 007 have to do with UVM and YOU?

james-bond-007-logo mp_007-1

Well, read on to find out:

Consider a peripheral IP such as SPI:

SPI_single_slave.svg

A sample Master implementation in RTL is available via OpenCores.org  Below is a link to the full specification if desired.

Focusing on the register portion of the spec alone:

Untitled
Delving into SPI Control Register:

spi_spec_1

 

Now, if you want to verify these register implementation including their access restrictions, write-read paths etc. using UVM, that can be a lot of code to write. Good news is we can automate this and that too for FREE* (For Mentor Questa users in this case).

First step would be to create a simple XL sheet with these register definitions as below:

spi_spec_as_CSV_XL

 

Do you think that’s some work as well? Why not download it for free from here?

Now, what’s next? Well, let’s invoke Questa’s Register Assistant:

RAssist_1

 

Then you have few options to choose the UVM version for instance:

vreg_wind

 

Take a look at the generated UVM code:

 

4

 

Also look closely at the SPI CTRL register generated code:

RAssist_3

Wow, that’s lot of automation for a single mouse click:mouse-click

Hold on, that’s not all, Questa does more – it builds the entire reg-model, configures each register as per the specification (ref. CSV file):

5

 

And finally it also does the “mapping” of each register:

6

 

So we are ready to GO! Let’s write a simple, dummy test as an experiment:

7

 

Note: this is part-1 of this “pictorial blog” on this topic:

10

 

Let’s take a look at the UVM run results:

8

 

So, What’s up?

9

 

As a recap – Questa’s Register Assistant is indeed your friendly “MoneyPenny” if you wish 🙂

MP_007

 

Use the CSV file format and automate your UVM code on the go!

11

Have a great 2015 ahead. Do contact us via training@cvcblr.com if you need a hands-on UVM session.

Here are the download links for the SPI IP:

 

 

Dec 27

Free-UVM-training-CVC-at-10: Go2UVM – Hands-on session

Free-UVM-training-CVC-at-10: Go2UVM Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 30 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register athttp://goo.gl/forms/39mWKsRbHY

Do you share any of the following concerns about UVM?

  • I know SystemVerilog and use it for TBs, but UVM is too complicated I feel
  • Is there a simple way to get started with UVM without having to go through 5-days (or more) training?
  • My Testbenches are really small and simple and UVM is way too complex for me
  • I develop traces to test my SVA (assertion) models, UVM is too complex, is it still “Universal” BTW?
  • I design & verify DSPs, UVM infrastructure sounds like overkill to me

Many of our customer do ask us the above. This is where CVC has put in deep OOP skills to assist and developed a simple Go2UVM package.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/39mWKsRbHY

Agenda:

  • Registration
  • Speaker introduction
  • Presentation
  • Networking with high-tea
  • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/39mWKsRbHY

Dec 27

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 29 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register at: http://goo.gl/forms/YkQoslRECj

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog and UVM. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space.

Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC’s VSV course as a wise step towards the same.

However when it comes to the production use, plain System Verilog falls behind in certain key areas.

Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is, technical attempt to challenge a solid DV engineer with decent SV skills.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/YkQoslRECj

Agenda:

  • • Registration
  • • Speaker introduction
  • • Presentation
  • • Networking with high-tea
  • • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/YkQoslRECj

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