Category Archive: Uncategorized

Feb 14

Waves2UVM – a Go2UVM app

For long, engineers needed an easy and scalable way to capture timing diagrams as part of their design specifications. There have been few commercial tools to help in this task. A relatively new tool named WaveDrom has been developed as an open-source JSON based solution for this. Quoting WaveDrom.com site:

WaveDrom draws your Timing Diagram or Waveform from simple textual description.
It comes with description language, rendering engine and the editor.
WaveDrom editor works in the browser or can be installed on your system.
Rendering engine can be embeded into any webpage.

So essentially when you are creating a new design specification and want to capture the timing relationship as a waveform, this utility can be very handy. For instance, below is a screenshot of ARM APB 2.0 specification (for Figure 3-4 in ARM specification):

The above diagram is very easy to create using JSON like syntax with WaveDrom editor – we will offer a download of the JSON file soon here for APB 2.0 specification. For many seasoned digital designers, a diagram such as above is a great source of reference to create:

  • Stimulus (i.e. apply the signal transitions as found in the specification to DUT – Design Under Test)
  • Checks – assertions in the form of SystemVerilog Assertions (SVA) for instance.

As part of our mission to widen UVM adoption across teams, we developed a tiny “app” that reads WaveDrom file and creates a UVM Test through Go2UVM Test API. With this app (Soon to be released along with latest Go2UVM 2017.01 release), one can input this waves.wd file and get a SystemVerilog-UVM test that can be run on a compliant DUT (RTL model for instance). The usage is quite straightforward:

perl $VW_GO2UVM_HOME/bin/vw_dvc_wd_apps.pl

The above app creates the following infrastructure necessary to reproduce the same timing diagram in a typical UVM simulation:

  • SystemVerilog interface file
  • Go2UVM Test that toggles wires as per the specification in the WaveDrom file
  • Top file that instantiates the test, connects the interface etc.
  • Makefile to run on all popular EDA tools.

 

Some of the screenshots from the app when ran on an APB 2.0 waves is below:

 

Go2UVM Test:

So as we are about to roll-out our latest Go2UVM library 2017.01 during DVCon USA 2017, there is a lot to look forward to! Stay tuned for more updates.

 

 

 

Nov 11

Handling variable delays in SystemVerilog Assertions

Have you got a modern design that has dynamic, variable latency bet’n request and response? Do you want to model that behavior in your verification code using SystemVerilog? Assertions are great way to capture such temporal requirements and verify them in simulations.

A more formal requirement
// After “start_sig” goes high
// within a variable delay of “var_del” clock cycles
// signal “end_sig” should go high

A first-cut SVA implementaion would look like below:

start_sig |-> ##[1:var_del] end_sig

However SVA as in IEEE 1800-2012 does NOT allow variable delays in properties/sequences. That would mean that assuming the var_del is a variable (int/integer/logic vector etc.) the above code won’t compile 🙁

 A work-around is to use local variable and count.

The core code is below:

sva_var_del

So what’s happening?

Line-3: Once you see a HIGH on start_sig, save the current value of var_del (Remember it is a variable, could change during the course of checking this transfer) in a local variable (v_cnt)

Line-4: Start decrementing v_cnt value once per clock (Till.. see next line)

Line-5: As soon as you see end_sig make sure your transfer did NOT timeout/expire

For all FSM lovers, here is the logic as a bubble diagram:

sva_var_del_fsm-png

In this example we have implemented that logic inside a “checker” (a new construct in SV) and make it easy for end users.

Now how do we “verify” this logic? Well, let’s use UVM trace with Go2UVM. One of the key benefits of Go2UVM is that while testing an assertion/checker for proper functionality, one could predict the errors and report them with SVUnit’s report-mock feature.

See go2uvm_tb_src/vw_var_del_in_sva_uvm.sv and look for expect_error API usage. We use that prediction for an intended fail trace and in the log file you will see the test still passes (as expected) despite the presence of an UVM_ERROR (again note that the test intentionally introduces errors and expects the SVA to flag it appropriately).

You can download the fully ready code as a tar ball below:

Handling Variable Delays in SVA & Go2UVM trace
3.6 KiB
20 Downloads
Details

Files Description:

UVM Trace –> go2uvm_tb_src/vw_var_del_in_sva_uvm.sv
SVA code –> sva_src/vw_var_del_in_sva.sv

To run;

cd run_dir
make cvc2 (for Questa). Other targets are available for other tools as we use a generic Makefile from: Generic Makefile for UVM

Aug 05

“Practical UVM” – new book now available!

A new book titled “Practical UVM” is now available on Amazon. The author is Srivatsa Vasudevan, Principal Engineer, Synopsys, USA. He is also currently serving as co-chair TPC DV track at DVCon India.With quotes from Janick @Synopsys and Srini @CVC this book is definitely worth a deep look for all UVM enthusiasts.

Janick Bergeron: 

In this book, you will find step-by-step instructions, coding guidelines, debugging features of UVM explained clearly using examples.The book covers the changes from UVM-1.1d to UVM 1.2 and also the changes between the 1.2 version and the upcoming IEEE 1800.2 UVM standard.

Srinivasan Venkataramanan 

As a seasoned engineer and co-author of DV books myself, I was impressed when I reviewed this book to find several interesting differences between how Srivatsa approaches the problem of UVM adoption and the way I have been doing it for my customers.  In helping him get this book in its current form, I have learned a lot and I think Practical UVM addresses several shortcomings of existing books in this topic which makes it a great reference for all DV engineers using UVM.

Efforts are ON to bring out an Indian edition of this book shortly, so stay tuned!

https://www.amazon.com/Practical-UVM-Srivatsa-Vasudevan/dp/0997789603

Practical_UVM_book_frontPractical_UVM_book_back

Jul 08

Open-source GPU decode block gets open-source Go2UVM Test!

If you are tracking the GPU industry and academia – there is a nice open-source GPU named MIAOW  miaow_GPU_logo

An abstract architecture of this GPU looks as below:

miaow_GPU_arch

The design seems to be well structured and RTL coded nicely, organized well etc. However, as with many of these open-source hardware models that we find on the web, the verification with a testbench (simulation) is done in a loose manner. For instance we looked at the decode block in this GPU and the testbench is a simple Linear TB. We decided to port this to UVM via Go2UVM package to demonstrate how easy it really is to migrate to UVM from Verilog.

You can download the open-source GPU’s decode block and Go2UVM test from here:

Open-source GPU - Miaow - Decode Blk - Go2UVM test
2.4 MiB
54 Downloads
Details

On top of the recently released Go2UVM 2015.06 release, we added productivity “apps” to generate all the necessary code to get going with UVM in minutes – given a RTL. For instance we created a DVC_Go2UVM app that runs on popular Aldec’s Riviera-PRO simulator and generates Go2UVM infrastructure on a push-of-a-button. Specifically this app creates:

  • SystemVerilog interface for the given RTL top module
  • Top level TB module with DUT instantiated, connected
  • Automates standard UVM run_test() mechanism to automate calling of components’ tasks (also known as Phasing in UVM)
  • Creates a test.svi file that user can add the specific test scenario

Among these files the only file user needs to bother/tweak is the test.svi to capture necessary test sequence. In a typical RTL DUT, a testcase stimulus has 2 basic parts: RESET & MAIN. We managed to port the GPU’s decode tb to Go2UVM reset phase as below:

gpu_rst_ph_g2u

 

It is useful to appreciate that UVM automates calling of these tasks defined in a class based test provided we follow a standard naming convention – also known as Phasing in UVM. To get little deeper – with Go2UVM package, one does NOT have to bother about raising and dropping objections – the package does that for you! If you are new to this UVM objection mechanism, a good read is at: New to UVM? Wonder why it exits at time zero?

Now the main phase looks as below:
gpu_main_ph_g2u

As one can appreciate – except for minor syntax changes, the original, plain Verilog Test and the corresponding UVM test with Go2UVM look very similar indeed!

If you can start seeing the benefits of moving to UVM with Go2UVM – great, here is a treat for your eyes:

gpu_g2u_log

As you can see above, debugging with UVM becomes lot easier – as the file name, line number, time of the message etc. come out automatically in UVM!

You can download the open-source GPU’s decode block and Go2UVM test from here:

Open-source GPU - Miaow - Decode Blk - Go2UVM test
2.4 MiB
54 Downloads
Details

Jun 11

Debug UVM factory with these great tips!

We recently wrote an article for Mentor Graphics’s popular Verification Horizons magazine, June 2016 | Volume 12, Issue 2

Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best practices.

Given the major adoption of UVM across the globe and across the industry, advanced users are looking for tips and tricks to improve their productivity. UVM does define a structured framework for building complex testbenches. It is built on strong OOP principles and design patterns using underlying SystemVerilog language features. This strong OOP nature presents certain challenges to the end users. Recall that many Design-Verification (DV) engineers come from hardware, electronics backgrounds and not heavy Software backgrounds. Hence at times it gets tricky for users to debug UVM based testbenches when things do not work as expected.

In this article the authors share their long experience of assisting customers with run time debug of common UVM issues and potential solutions to them. During our various training and consulting engagements using UVM we have seen DV engineers struggling to debug relatively simple UVM issues. It will be unfair to blame the users as many a times, the error messages are cryptic and do not point to the actual source code, rather somewhere from the base classes, making the debug difficult. We have captured a series of such common issues and error messages into a collateral form that we call “UVM Vault”. As part of our QVP engagement with Mentor Graphics, we are integrating this UVM Vault to Questa® in the near future.

Download the UVM Debug techniques as PDF below:

UVM factory debug techniques - our article from Mentor's Verification Horizons magazine
1.0 MiB
126 Downloads
Details

You can read full Horizons article at: https://verificationacademy.com/verification-horizons/june-2016-volume-12-issue-2

Jun 09

UVM tit-bit – m_sequencer vs. p_sequencer

Often we see users asking: what are the 2 sequencer pointers – m_sequencer vs. p_sequencer ?

Having trained 1000s of engineers in this domain, CVC (http://www.cvcblr.com) is glad to release attached PDF for free users to appreciate this key feature. So go ahead enjoy reading the same!

UVM m_sequencer vs. p_sequencer
UVM m_sequencer vs. p_sequencer
CVC_m_sequencer_vs_p_sequencer.pdf
Version: 1.0
957.4 KiB
167 Downloads
Details

 

 

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