Category Archive: UVM1.2

Feb 03

Simplifying UVM messaging – `g2u_display()

As part of our goal to making UVM easy-to-use, we keep adding more features to the Go2UVM library. One of the recent additions is “Simplified messaging in UVM”. Intention is to bring the benefits of UVM messaging to all Verilog-aware engineers in the easiest way. Looking back at Verilog’s native $display(), it is the most used debug techniques in simulation based verification. It is easy to use, concise and almost every Verilog aware engineer is used to this tiny feature. However it does have its deficiencies, especially when it comes to debugging someone else’s code and when the project is large. Some of the most common issues with plain old $display() are:

  • Lack of $time in-built – i.e. since Verilog is mostly dealing with timed models, it is very useful to have the simulation time available with every message. One can add it manually to every $display() – but that’s work!
  • No FILE & LINE number information from $display() – as SystemVerilog added 2 handy macros `__FILE__ to get the file name, and `__LINE__ macro to retrieve the line number. This has been a standard debug technique in software for ages especially when the code is expected to change hands often.

UVM has added several APIs and macros to resolve the above issues and the popular macros are:

  • `uvm_info (ID, MSG, VERBOSITY)
  • `uvm_error (ID, MSG)

However, a uninitiated Verilog like engineer finds the above bit strange, especially the ID part of the macros. With no strict guidelines from UVM documentation on what to use as ID, teams tend to misuse this quite a bit. Seasoned engineers tend to use built-in uvm_object::get_name() as ID as that tends to make the log file comprehendible and correlates quickly to the objects in UVM. And the VERBOSITY – many a times engineers use UVM_MEDIUM. Given that SystemVerilog allows default values for macro arguments, one would hope and expect that the UVM library would add a default value for this argument. – but as of now it does NOT – forcing users to add this to every display message by hand! Let’s look at few sample UVM message code:

`uvm_info (get_name(), “Hello World”, UVM_MEDIUM)

`uvm_info (get_name(), “Generated a packet”, UVM_HIGH)

`uvm_info (get_name(), $sformatf (“Writing to addr: 0x%x data: 0x%x”,

x0.addr, x0.data), UVM_MEDIUM)

 

That’s bit of a code for first time UVM engineers. How about we simplify the same as below:

 

`g2u_display (“Hello World!”)

`g2u_display (“Generated a packet”, UVM_HIGH)

`g2u_display ($sformatf (“Writing to addr: 0x%x data: 0x%x”,

x0.addr, x0.data))

 

That is handy and neat! Under-the-hood we still call the same UVM API (uvm_report_info() for instance). So what happens?

  1. ID : we use get_name() automatically (And a nice, built-in workaround to handle scopes outside uvm_object, don’t worry!)
  2. VERBOSITY – we use default argument to the macro to use UVM_MEDIUM

 

So with Go2UVM, adopting UVM becomes easier and simple.

Stay tuned for more updates in next major release of Go2UVM!

 

Aug 05

“Practical UVM” – new book now available!

A new book titled “Practical UVM” is now available on Amazon. The author is Srivatsa Vasudevan, Principal Engineer, Synopsys, USA. He is also currently serving as co-chair TPC DV track at DVCon India.With quotes from Janick @Synopsys and Srini @CVC this book is definitely worth a deep look for all UVM enthusiasts.

Janick Bergeron: 

In this book, you will find step-by-step instructions, coding guidelines, debugging features of UVM explained clearly using examples.The book covers the changes from UVM-1.1d to UVM 1.2 and also the changes between the 1.2 version and the upcoming IEEE 1800.2 UVM standard.

Srinivasan Venkataramanan 

As a seasoned engineer and co-author of DV books myself, I was impressed when I reviewed this book to find several interesting differences between how Srivatsa approaches the problem of UVM adoption and the way I have been doing it for my customers.  In helping him get this book in its current form, I have learned a lot and I think Practical UVM addresses several shortcomings of existing books in this topic which makes it a great reference for all DV engineers using UVM.

Efforts are ON to bring out an Indian edition of this book shortly, so stay tuned!

https://www.amazon.com/Practical-UVM-Srivatsa-Vasudevan/dp/0997789603

Practical_UVM_book_frontPractical_UVM_book_back

Jul 20

Advanced UVM tutorial (from DVCon US 2016) slides now available

As we promote UVM from basics to advanced user base across the globe, we are glad to share our UVM tutorial slides covering advanced topics. This tutorial was presented at recent DVCon USA 2016 along with Synopsys and others. Referring to the event summary at: http://events.dvcon.org/events/proceedings.aspx?id=199-1-T 

Debugging UVM testbenches can be extremely difficult because errors often appear in lines of SystemVerilog code that make up the UVM package, as opposed to the user written code. Most of these errors can easily be eliminated by following a structured approach to debugging that targets these common errors first. This part of the tutorial will walk through run-time errors and built in debugging features in UVM and how to use them.

You can download the PDF from here for free:

VerifWorks's UVM Tutorial at DVCon USA 2016
VerifWorks's UVM Tutorial at DVCon USA 2016
VW_UVM_tutorial_DVCon_US_2016.pdf
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May 06

Free download of different UVM class library versions

As the premier GO-TO place for the industry’s standard verification methodology – UVM, Go2UVM.org is glad to make the following versions available for free download (distributed under Apache 2.0 license, below. We will add more updates to these as it becomes available.

Download UVM 1.0p1 Class library

Download UVM 1.1a Class library

Download UVM 1.1b Class library

Download UVM 1.1c Class library

Download UVM 1.1d Class library

Download UVM 1.2 Class library

 

Below is a brief timeline/history of UVM evolution.

 

UVM_timeline

Dec 27

Free-UVM-training-CVC-at-10: Go2UVM – Hands-on session

Free-UVM-training-CVC-at-10: Go2UVM Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 30 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register athttp://goo.gl/forms/39mWKsRbHY

Do you share any of the following concerns about UVM?

  • I know SystemVerilog and use it for TBs, but UVM is too complicated I feel
  • Is there a simple way to get started with UVM without having to go through 5-days (or more) training?
  • My Testbenches are really small and simple and UVM is way too complex for me
  • I develop traces to test my SVA (assertion) models, UVM is too complex, is it still “Universal” BTW?
  • I design & verify DSPs, UVM infrastructure sounds like overkill to me

Many of our customer do ask us the above. This is where CVC has put in deep OOP skills to assist and developed a simple Go2UVM package.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/39mWKsRbHY

Agenda:

  • Registration
  • Speaker introduction
  • Presentation
  • Networking with high-tea
  • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/39mWKsRbHY

Dec 27

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

Free-UVM-training-CVC-at-10: Why UVM? Hands-on session

CVC is celebrating 10 years this Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! While the celebrations are just starting, we want all of YOU, the UVM users to be part of it too! Hence, here is our 10th year gift to the DV/UVM community:

10 days of continuous UVM training, for free to all those interested.

Schedule: 29 December 2014, 15.00 to 18.00 (3 PM to 6 PM)

Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2 

Cost:  FREE

Register at: http://goo.gl/forms/YkQoslRECj

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog and UVM. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space.

Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC’s VSV course as a wise step towards the same.

However when it comes to the production use, plain System Verilog falls behind in certain key areas.

Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is, technical attempt to challenge a solid DV engineer with decent SV skills.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/

Hurry, limited seating, first-come-first-serve basis

Register at: http://goo.gl/forms/YkQoslRECj

Agenda:

  • • Registration
  • • Speaker introduction
  • • Presentation
  • • Networking with high-tea
  • • Hands-on lab session, solve the SystemVerilog usage puzzle!

Register via: http://goo.gl/forms/YkQoslRECj

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