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For long, engineers needed an easy and scalable way to capture timing diagrams as part of their design specifications. There have been few commercial tools to help in this task. A relatively new tool named WaveDrom has been developed as an open-source JSON based solution for this. Quoting WaveDrom.com site: WaveDrom draws your Timing Diagram or …

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As part of our goal to making UVM easy-to-use, we keep adding more features to the Go2UVM library. One of the recent additions is “Simplified messaging in UVM”. Intention is to bring the benefits of UVM messaging to all Verilog-aware engineers in the easiest way. Looking back at Verilog’s native $display(), it is the most used debug …

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For those using UVM in live projects and looking to see what’s next in DV – here is an opportunity to learn (for free) UVM Registers -a definitive first step to “Portable Stimulus”. Accellera’s PSS working group is working on defining how a portable test specification can be defined and is expected to be the next …

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Have you got a modern design that has dynamic, variable latency bet’n request and response? Do you want to model that behavior in your verification code using SystemVerilog? Assertions are great way to capture such temporal requirements and verify them in simulations. A more formal requirement // After “start_sig” goes high // within a variable …

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Given the widespread usage of UVM across the globe, many first timers to UVM find it hard to remember all relevant options to their favourite simulator to get going with UVM. Our Go2UVM approach is addressing this very issue via a generic Makefile. Given most of the VLSI engineers are familiar with Makefile use model, …

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A new book titled “Practical UVM” is now available on Amazon. The author is Srivatsa Vasudevan, Principal Engineer, Synopsys, USA. He is also currently serving as co-chair TPC DV track at DVCon India.With quotes from Janick @Synopsys and Srini @CVC this book is definitely worth a deep look for all UVM enthusiasts. Janick Bergeron:  In this …

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Aug 05

“Practical UVM” – new book now available!

A new book titled “Practical UVM” is now available on Amazon. The author is Srivatsa Vasudevan, Principal Engineer, Synopsys, USA. He is also currently serving as co-chair TPC DV track at DVCon India.With quotes from Janick @Synopsys and Srini @CVC this book is definitely worth a deep look for all UVM enthusiasts. Janick Bergeron:  In this …

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Jul 20

Advanced UVM tutorial (from DVCon US 2016) slides now available

As we promote UVM from basics to advanced user base across the globe, we are glad to share our UVM tutorial slides covering advanced topics. This tutorial was presented at recent DVCon USA 2016 along with Synopsys and others. Referring to the event summary at: http://events.dvcon.org/events/proceedings.aspx?id=199-1-T  Debugging UVM testbenches can be extremely difficult because errors often …

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Jul 08

Open-source GPU decode block gets open-source Go2UVM Test!

If you are tracking the GPU industry and academia – there is a nice open-source GPU named MIAOW   An abstract architecture of this GPU looks as below: The design seems to be well structured and RTL coded nicely, organized well etc. However, as with many of these open-source hardware models that we find on …

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Jun 19

Go2UVM package 2016.05 now available

With UVM taking center stage in VLSI design verification at large, more and more new users are looking at adopting UVM. While the existing ASIC DV teams are getting more and more sophisticated with their UVM flow, Go2UVM.org serves as the GO-TO site for advanced use cases, debug flows etc. Specifically we have released 2 …

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Jun 11

Debug UVM factory with these great tips!

We recently wrote an article for Mentor Graphics’s popular Verification Horizons magazine, June 2016 | Volume 12, Issue 2 Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best …

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Jun 09

UVM tit-bit – m_sequencer vs. p_sequencer

Often we see users asking: what are the 2 sequencer pointers – m_sequencer vs. p_sequencer ? Having trained 1000s of engineers in this domain, CVC (http://www.cvcblr.com) is glad to release attached PDF for free users to appreciate this key feature. So go ahead enjoy reading the same!    

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