Tag Archive: EDA

Oct 27

Generic Makefile for UVM simulations

Given the widespread usage of UVM across the globe, many first timers to UVM find it hard to remember all relevant options to their favourite simulator to get going with UVM. Our Go2UVM approach is addressing this very issue via a generic Makefile. Given most of the VLSI engineers are familiar with Makefile use model, we provide a free to use (even for commercial deployment) Makefile here:

[wpfilebase tag=file id=18 /]

So how does this work?

  1. Create a text file named “flist” that contains names (and paths as necessary) of all the design and Testbench files.
  2. Choose your favourite simulator – Synopsys, Cadence, Mentor or Aldec – we support all of them in single Makefile.
  3. On a terminal type: make cvc2_gui TOP=my_chip_uvm_tb_top TEST=my_uvm_test

That’s it!

Here are different EDA tool supported along with our Makefile target names:




Apr 16

Run UVM Hello World in 10 Seconds — The Fastest Way to Get Started with UVM

Run UVM Hello World in 10 Seconds — The Fastest Way to Get Started with UVM

Guest Blogger, Victor Lyuboslavsky, Victor EDA


Yes, you can run a UVM Hello World simulation in the next 10 seconds: No need to install any EDA tool at your end, all within your favourite web browser, here you go:

1. Open the EDA Playground UVM Hello World example on a separate page.

2. Click Login in the top right corner and log in with your favorite social media account.

3. When the page reloads, you’ll see the UVM Hello World code example again.

4. Click Run and watch real-time output in the bottom pane.

5. Done! Now come back to this page.

UVM_HW_EDAP UVM stands for Universal Verification Methodology. UVM is currently the most popular methodology for verifying FPGA and ASIC design. This example uses the SystemVerilog UVM library.

We will soon follow-up with next entry to delve into a “realistic” example, feel free to add your comments!

Guest Blogger, Victor Lyuboslavsky, Victor EDA