Tag Archive: UVM

Dec 07

UVM Registers – first step to Portable Stimulus, free training

For those using UVM in live projects and looking to see what’s next in DV – here is an opportunity to learn (for free) UVM Registers -a definitive first step to “Portable Stimulus”. Accellera’s PSS working group is working on defining how a portable test specification can be defined and is expected to be the next big wave in DV space.

CVC, a global leader in VLSI Design-Verification training is pleased to offer a free half-a-day training on UVM RAL/Registers. It is free of cost, but registration is must.

Register at: https://goo.gl/forms/2UQvmI90Lp6dgKwk2

When? Dec 17th, 2016 Saturday, 10 AM – 1 PM (Indian Standard Time)

Address: http://www.fb.com/cvc.uvm/about 

Cost:  FREE

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/ 

Hurry, limited seating, first-come-first-serve basis.

Agenda:

• UVM introduction

• Capturing registers in UVM

• Using XL sheet to capture Register Specification

• Brief look at IP-XACT for register specification

• Case studies: popular IPs and their register specifications

• Demo: VerifWorks DVCreate PSS tool to generate UVM-RAL model from IP-XACT

Register via: https://goo.gl/forms/2UQvmI90Lp6dgKwk2

 

 

 

Oct 27

Generic Makefile for UVM simulations

Given the widespread usage of UVM across the globe, many first timers to UVM find it hard to remember all relevant options to their favourite simulator to get going with UVM. Our Go2UVM approach is addressing this very issue via a generic Makefile. Given most of the VLSI engineers are familiar with Makefile use model, we provide a free to use (even for commercial deployment) Makefile here:

Makefile for compiling and running any UVM simulation with any EDA tool
2.4 KiB
81 Downloads
Details

So how does this work?

  1. Create a text file named “flist” that contains names (and paths as necessary) of all the design and Testbench files.
  2. Choose your favourite simulator – Synopsys, Cadence, Mentor or Aldec – we support all of them in single Makefile.
  3. On a terminal type: make cvc2_gui TOP=my_chip_uvm_tb_top TEST=my_uvm_test

That’s it!

Here are different EDA tool supported along with our Makefile target names:

go2uvm_makefile_targets